1. Field of the Invention
The present inventive concept relates to an electrostatic discharge protection (ESD) device and system. More particularly, the inventive concept relates to a semiconductor controlled rectifier (SCR)-based ESD device for protecting the monitoring device more efficiently.
2. Description of the Related Art
ESD damage has become one of the main reliability concerns of integrated circuit (IC) products. Various electronic devices have been used as ESD protection devices to protect the complementary metal oxide semiconductor (CMOS) integrated circuits from damage. Referring to FIG. 1A and FIG. 1B, the ESD protection systems 100 are illustrated according to the prior art. One diode 110 is arranged between the pad 102 and the pad 104, and another diode 110 is arranged between the pad 102 and the pad 106. Specifically, the pad 102 is an input/output (I/O) pad, the pad 104 is a VDD voltage pad, and the pad 106 is a VSS voltage pad. The analog transceiver 130 is arranged beside the two diodes 110 and between the pads 104 and 106. As shown in FIG. 1A, an ESD path SA is provided to discharge the ESD current for the ESD protection system 100.
FIG. 1B illustrates another ESD protection system 100. As shown in FIG. 1B, two SCR devices 120 are included to replace the two diodes of FIG. 1A. The two SCR devices 120 of FIG. 1B have the same capacitive load as the two diodes 110 of FIG. 1A. However, compared to the ESD protection system 100 of FIG. 1A, another ESD path SB is provided by the ESD protection system 100 of FIG. 1B. Therefore, the ESD protection system 100 of FIG. 1B has better performance and capabilities in discharging the ESD current than the ESD protection system 100 of FIG. 1A. In addition, a power clamp is needed for the ESD protection system 100 of FIG. 1A, but the power clamp is not needed by the ESD protection system 100 of FIG. 1B due to its active turn-on capability.
Regarding the diode 110, since the N/P+ junction is a shallow trench isolation (STI), the current flows in the deep area of the junction. As such, the turn-on speed of the ESD protection system 100 is slow due to the STI of the diode 110. Therefore, another gated diode 200 is provided. FIG. 2 is a schematic diagram illustrating a gated diode 200 according to the prior art. As shown in FIG. 2, the doping regions 220, 222 and 224 are disposed in the well 210. Specifically, the well 210 is an N-type well, the doping regions 220 and 224 are N-type doping regions, and the doping region 222 is a P-type doping region. In addition, the poly-silicon region 230 is disposed on the well 210 and located between the doping regions 220 and 222. The poly-silicon region 232 is disposed on the well 210 and located between the doping regions 222 and 224. Nodes 240, 242 and 244 are disposed on the doping regions 220, 222 and 224 respectively for biasing the gated diode 200. The poly-silicon region 230 is connected to the node 240, and the poly-silicon region 232 is connected to the node 244. For example, node 242 is the anode, and node 244 is the cathode. Since the poly-silicon regions 230 and 232 connect the biasing nodes to the well 210, the current of the gated diode 200 flows in a surface area rather than a deep area. Accordingly, the turn-on speed is improved. However, the capacitive load increases due to the junction between the doping region 222 and the poly-silicon region 230 or 232. In addition, the power clamp is still needed for the gated diode 200.
Therefore, a novel ESD device is needed to increase the turn-on speed without increasing the capacitive load. In addition, when a monitoring device is utilized to monitor the turn-on speed of the ESD device, it is often damaged by the ESD current. As such, protecting the monitoring device is also another problem in designing and manufacturing a novel ESD device.